Makefile Variables Example

Make-File Instruction for Variables

If we use the GNU, then we should add one line to the make-file before debugging. It is so useful that we should do it all the time and in every make-file that we create.

print-%: ; @echo $*=$($*)

This line allows us to quickly get the value of any variable in the make-file. For example, if we want to know the value of a variable with the name “SOURCE_FILES” then we just need to enter: make print-SOURCE_FILES. If we are using GNU Make 3.82 or higher, we do not even need to change the assembly itself and enter the following:

make --eval="print-%: ; @echo $*=$($*)" print-SOURCE_FILES

So we get the value of SOURCE_FILES. The “–eval” adds the make-file to our string without changing it, which is a very convenient way if it is necessary to keep the assembly intact.

How does this work?


print-%: ; @echo $*=$($*)
This defines a template on which instead of the sign “%” may be the sought variable. So when we ask for a printout of the SOURCE_FILES to, then this rule will be fulfilled, as % will be is implied by our variable of SOURCE_FILES. The @echo $ * = $ ($ *) command is a command that runs under the command print-%. A semicolon is used to separate the two commands from each other and eliminates the need to write it in two rows. However, it looks like this in a more traditional way:

@echo $*=$($*)

As we can see, the use of semicolons slightly simplifies everything. The automatic variable $* corresponds to %  in the print-% (when we run “print-SOURCE_FILES” our variable $* will correspond to SOURCE_FILES). Thus, $* contains the name of the variable that we want to output. And $($ *) is the value of the variable whose name is stored in $*. For example, $* gets the name of the SOURCE_FILES, and GNU Make gets the value stored in $(SOURCE_FILES). Saving the content of one variable to another variable can be a very useful method for many make-files.

Thanks for your attention!

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